learning.TVM Stack High-Level Differentiable IR Tensor Expression and Optimization Search Space LLVM, CUDA, Metal VTA Edge FPGA Cloud FPGA ASIC Optimization AutoTVM Device FleetExisting Deep Learning Design in Verilog VerilatorToward Unified IR InfraOverview of New IR Infra Single unified module/pass, type system, with function variants supportCompilation Flow under the New Infra IRModule (relay::Function) print(mod[”te_add_one”].args) Use hybrid script as an alternative text format Directly write pass, manipulate IR structures Accelerate innovation, 
 e.g. use (GA/RL/BayesOpt/your favorite ML method)

835), mate10/mate10pro (kirin 970), p20/p20pro (kirin 970) -target=arm64-linux-android -mattr=+neon llvm firefly rk3399, rock960, ultra96 -target=aarch64-linux-gnu -mattr=+neon rasp3b (bcm2837) -targ (mali g71) N/A FPGA vta pynq, ultra96 N/A sdaccel Out-of-tree support or WIP: Hexagon DSP (via llvm), Ascend NPU, and more Green: Linaro 96BoardsLinaro for TVM ● Linaro AI/ML group can be a good fit

“-shared”, “-fPIC”, “-m32”] b. python tensorflow_blur.py to get the .log c. Use the .log, with target=“llvm –mcpu=i686 –mtriple=i686-linux-gnu” then TVM_NDK_CC=“clang –m32” python tf_blur.py���������������

VMCompiler() with tvm.autotvm.apply_graph_best("resnet50_v1_graph_opt.log"): vm = vmc.compile(mod, "llvm") vm.init(ctx) vm.load_params(params) data = np.random.uniform(size=(1,