linearly interpolated between the given setpoints binary A binary signal restricted to only 2 states clock A clocked signal that repeatedly transitions from high to low, with a period, and an optional pulse @100 WU is Waiting WB is Processing @300 WB is Waiting @enduml @startuml clock "Clock_0" as C0 with period 50 clock "Clock_1" as C1 with period 50 pulse 15 offset 10 binary "Binary" as B concise "Concise" 2 Binary and Clock 10 TIMING DIAGRAM A is 3 @300 R is Waiting A is 1 @enduml [Ref. QA-14631, QA-14647 and QA-11288] 10.2 Binary and Clock It’s also possible to have binary and clock signal, using

line signal designed to show the transition from one state to another (can have many states). • clock: A 'clocked' signal that repeatedly transitions from high to low • binary: A specific signal restricted WB is Waiting @enduml 9.2 Binary and Clock It's also possible to have binary and clock signal, using the following keywords: • binary • clock @startuml clock clk with period 1 binary "Enable" as EN point by using the as keyword and starting the name with a :. @XX as : @startuml clock clk with period 1 binary "enable" as EN concise "dataBus" as db @0 as :start @5 as :en_high @10 as

line signal designed to show the transition from one state to another (can have many states). • clock: A 'clocked' signal that repeatedly transitions from high to low • binary: A specific signal restricted WB is Waiting @enduml 9.2 Binary and Clock It's also possible to have binary and clock signal, using the following keywords: • binary • clock @startuml clock clk with period 1 binary "Enable" as EN point by using the as keyword and starting the name with a :. @XX as : @startuml clock clk with period 1 binary "enable" as EN concise "dataBus" as db @0 as :start @5 as :en_high @10 as

line signal designed to show the transition from one state to another (can have many states). • clock: A ’clocked’ signal that repeatedly transitions from high to low • binary: A specific signal restricted WB is Waiting @enduml 10.2 Binary and Clock It’s also possible to have binary and clock signal, using the following keywords: • binary • clock @startuml clock clk with period 1 binary "Enable" as EN point by using the as keyword and starting the name with a :. @XX as : @startuml clock clk with period 1 binary "enable" as EN concise "dataBus" as db @0 as :start @5 as :en_high @10 as

line signal designed to show the transition from one state to another (can have many states). • clock: A ’clocked’ signal that repeatedly transitions from high to low • binary: A specific signal restricted WB is Waiting @enduml 10.2 Binary and Clock It’s also possible to have binary and clock signal, using the following keywords: • binary • clock @startuml clock clk with period 1 binary "Enable" as EN point by using the as keyword and starting the name with a :. @XX as : @startuml clock clk with period 1 binary "enable" as EN concise "dataBus" as db @0 as :start @5 as :en_high @10 as

line signal designed to show the transition from one state to another (can have many states). • clock: A ’clocked’ signal that repeatedly transitions from high to low • binary: A specific signal restricted WB is Waiting @enduml 10.2 Binary and Clock It’s also possible to have binary and clock signal, using the following keywords: • binary • clock @startuml clock clk with period 1 binary "Enable" as EN point by using the as keyword and starting the name with a :. @XX as : @startuml clock clk with period 1 binary "enable" as EN concise "dataBus" as db @0 as :start @5 as :en_high @10 as

()two [ok] } }} " as choose choose -right-> " {{ salt {+ please wait operation in progress <&clock> [cancel] } }} " as wait wait -right-> " {{ salt {+ success congratulations! [ok] } }} " as success option ()one ()two [ok] } !enddefinelong !definelong _wait {+ please wait operation in progress <&clock> [cancel] } !enddefinelong !definelong _success {+ success congratulations! [ok] } !enddefinelong