RDBMSとNoSQLのメリットを併せ持つクラウドネイティブなNewSQLデータベース
「TiDB」をKubernetesで動かしてみよう!Transactions (分散トランザクション) Cloud Native (クラウドネイティブ志向) Minimize ETL (OLTP と OLAP のサポート) High Availability (高可用性) Open Source Conference 2022 Online/Spring 12 TiDB の特徴 Horizontal Scalability (水平拡張) Transactions (分散トランザクション) Cloud Native (クラウドネイティブ志向) Minimize ETL (OLTP と OLAP のサポート) High Availability (高可用性) Open Source Conference 2022 Online/Spring 13 TiDB の特徴 (Horizontal Scalability) TiDB Transactions (分散トランザクション) Cloud Native (クラウドネイティブ志向) Minimize ETL (OLTP と OLAP のサポート) High Availability (高可用性) Open Source Conference 2022 Online/Spring 16 TiDB の特徴 (MySQL Compatible Syntax) MySQL0 码力 | 71 页 | 6.65 MB | 1 年前3
KiCad 8.0 Calculator Toolsparameters. The models implemented are frequency-dependent, so they disagree with simpler models at high enough frequencies. This calculator is heavilly based on Transcalc. The transmission line types 1984. doi: 10.1109/TMTT.1984.1132616. Rolf Jansen, "High-Speed Computation of Single and Coupled Microstrip Parameters Including Dispersion, High-Order Modes, Loss and Finite Strip Thickness", IEEE Trans instruments where high performance and extended life is required and for which uninterrupted service is desired but not critical. Certain cosmetic imperfections are allowed. Class 3 High Reliability Electronic0 码力 | 8 页 | 360.88 KB | 1 年前3
PlantUML を使った UML の描き方 - PlantUML 言語リファレンスガイド(Version 1.2023.11)concise データの動きを表すための単純化された信号(メッセージに最適です) robust 状態の遷移を表すための複雑な線(複数の状態を作れます) clock period の時間間隔で high と low の状態を繰り返し遷移するクロック信号(pulse, offset を指定することもできます) binary 2 状態(バイナリ)に制限された信号 @ と is を用いて、状態の変化を記述できます。 binary "Binary" as B concise "Concise" as C robust "Robust" as R @0 C is Idle R is Idle @100 B is high C is Waiting R is Processing @300 R is Waiting PlantUML 言語リファレンスガイド (1.2023.11) 236 / 544 10.2 • binary • clock @startuml clock clk with period 1 binary "Enable" as EN @0 EN is low @5 EN is high @10 EN is low @enduml 10.3 メッセージ(相互作用) メッセージは、矢印構文を使います。 @startuml robust "ウェブブラウザ" as WB concise0 码力 | 545 页 | 7.75 MB | 1 年前3
PlantUML 1.2020.23 言語リファレンスガイド• binary • clock @startuml clock clk with period 1 binary "Enable" as EN @0 EN is low @5 EN is high @10 EN is low @enduml PlantUML 言語リファレンスガイド (1.2020.23) 138 / 305 9.3 メッセージ(相互作用) 9 タイミング図 9.3 "dataBus" as db @0 as :start @5 as :en_high @10 as :en_low @:start EN is low db is "0x0000" @:en_high EN is high @:en_low EN is low @:en_high-2 db is "0xf23a" @:en_high+6 db is "0x0000" @enduml PlantUML "0x0" addr is "0x03f" rw is low dv is 0 @:write_beg-3 en is high @:write_beg-2 db is "0xDEADBEEF" @:write_beg-1 dv is 1 @:write_beg rw is high @:write_end rw is low dv is low @:write_end+1 rw is low db0 码力 | 306 页 | 3.19 MB | 1 年前3
PlantUML を使った UML の描き方 - PlantUML 言語リファレンスガイド(Version 1.2020.22)• binary • clock @startuml clock clk with period 1 binary "Enable" as EN @0 EN is low @5 EN is high @10 EN is low @enduml PlantUML 言語リファレンスガイド (1.2020.22) 127 / 293 9.3 メッセージ(相互作用) 9 タイミング図 9.3 "dataBus" as db @0 as :start @5 as :en_high @10 as :en_low @:start EN is low db is "0x0000" @:en_high EN is high @:en_low EN is low @:en_high-2 db is "0xf23a" @:en_high+6 db is "0x0000" @enduml PlantUML "0x0" addr is "0x03f" rw is low dv is 0 @:write_beg-3 en is high @:write_beg-2 db is "0xDEADBEEF" @:write_beg-1 dv is 1 @:write_beg rw is high @:write_end rw is low dv is low @:write_end+1 rw is low db0 码力 | 294 页 | 3.11 MB | 1 年前3
Krita 5.2 マニュアル
screens, but it's very likely that your screen isn't exactly fitting sRGB, especially if you have a high quality screen, where it may be a bigger space instead. Device spaces are also why you should first working space, just like how you have the layers unmerged in the working file, or have it at a very high resolution. Sometimes, we apply aesthetic or 'look' spaces to an image as part of the editing process screen profiles. In such case, calibrating both screens to match sRGB profile (or another standard for high-end monitors if they both support it) can be a good solution. Soft-proofing When you need to match0 码力 | 1591 页 | 79.16 MB | 1 年前3
PlantUML を使った UML の描き方 - PlantUML 言語リファレンスガイド(Version 1.2021.1)• binary • clock @startuml clock clk with period 1 binary "Enable" as EN @0 EN is low @5 EN is high @10 EN is low @enduml PlantUML 言語リファレンスガイド (1.2021.1) 181 / 392 10.3 メッセージ(相互作用) 10 タイミング図 10 "dataBus" as db @0 as :start @5 as :en_high @10 as :en_low @:start EN is low db is "0x0000" @:en_high EN is high @:en_low EN is low @:en_high-2 db is "0xf23a" @:en_high+6 db is "0x0000" @enduml PlantUML @:write_beg-3 en is high @:write_beg-2 db is "0xDEADBEEF" @:write_beg-1 dv is 1 @:write_beg rw is high @:write_end rw is low dv is low @:write_end+1 rw is low db is "0x0" addr is "0x23" @12 dv is high @13 db is0 码力 | 393 页 | 4.27 MB | 1 年前3
PlantUML を使った UML の描き方 - PlantUML 言語リファレンスガイド(Version 1.2021.2)• binary • clock @startuml clock clk with period 1 binary "Enable" as EN @0 EN is low @5 EN is high @10 EN is low @enduml PlantUML 言語リファレンスガイド (1.2021.2) 184 / 398 10.3 メッセージ(相互作用) 10 タイミング図 10 "dataBus" as db @0 as :start @5 as :en_high @10 as :en_low @:start EN is low db is "0x0000" @:en_high EN is high @:en_low EN is low @:en_high-2 db is "0xf23a" @:en_high+6 db is "0x0000" @enduml PlantUML @:write_beg-3 en is high @:write_beg-2 db is "0xDEADBEEF" @:write_beg-1 dv is 1 @:write_beg rw is high @:write_end rw is low dv is low @:write_end+1 rw is low db is "0x0" addr is "0x23" @12 dv is high @13 db is0 码力 | 399 页 | 4.33 MB | 1 年前3
PlantUML 1.2021.3 言語リファレンスガイド• binary • clock @startuml clock clk with period 1 binary "Enable" as EN @0 EN is low @5 EN is high @10 EN is low @enduml PlantUML 言語リファレンスガイド (1.2021.2) 194 / 411 10.3 メッセージ(相互作用) 10 タイミング図 10 "dataBus" as db @0 as :start @5 as :en_high @10 as :en_low @:start EN is low db is "0x0000" @:en_high EN is high @:en_low EN is low @:en_high-2 db is "0xf23a" @:en_high+6 db is "0x0000" @enduml PlantUML @:write_beg-3 en is high @:write_beg-2 db is "0xDEADBEEF" @:write_beg-1 dv is 1 @:write_beg rw is high @:write_end rw is low dv is low @:write_end+1 rw is low db is "0x0" addr is "0x23" @12 dv is high @13 db is0 码力 | 412 页 | 4.46 MB | 1 年前3
KiCad 8.0 PCB Editorspace on a board layer (or a portion of a layer) in order to create ground and power planes, carry high currents, or to provide shielding. NOTE Some EDA tools have separate tools for creating "plane layers" the new targets. The following example custom rule sets a target length and skew for nets in the high_speed netclass. The target length is 100mm, and a DRC error will be raised if it is below 95mm or trace from a drilled pad or via. (rule "target length and skew" (condition "A.NetClass == 'high_speed'") (constraint length (min 95mm) (opt 100mm) (max 105mm)) (constraint skew (max0 码力 | 204 页 | 6.90 MB | 1 年前3
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