. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 7. 使用包、Crate 和模块管理不断增长的项目 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 7.2. 定义模块来控制作用域与私有性 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 7.3. 引用模块树中项的路径 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 7.5. 将模块拆分成多个文件 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

around 12–18 month releases due to various constraints. While Moore’s Law often drives an 18-month schedule, that still represents a significant improvement over five-year increments that end up averaging team hold planning sessions before each sprint?  Does each release and sprint have a defined schedule?  Are sprint and release durations consistent (e.g., all sprints are one month long)?  make certain that the requirements can be put on contract and are affordable based on funding, schedule, and technological constraints. Testers should take an active part in these discussions as well

Target-optimized graph Target-dependent Relay passes Intel x86 ARM CPU Nvidia GPU ARM GPU Schedule templates written in TVM Tensor IR .. More targets AutoTVM – Tuning the kernels Optimized Binary Target-independent Relay passes Target-optimized Int8 Relay Graph Intel x86 schedule ARM CPU schedule Nvidia GPU schedule ARM GPU schedule Relay Int8 Graph Target-dependent Relay layout opt© 2019, Amazon speedup on Inception asymmetric quantized model • Mobilenet requires depthwise convolution VNNI schedule • Symmetric model improves the speedup to 2.8x© 2019, Amazon Web Services, Inc. or its Affiliates

于 TVM TOPI Schedule Primitives & Optimizations Symbols NNVM & Param Frontends Operators Algorithm &Schedule CUDA TOPI Backends Machine Learning Automated Optimizer Schedule explorer Cost out operation w How to compute. @autotvm.register_ topi_schedule(schedule_conv2d_nchw，pvr, [direct]) convolution def schedule_conv2d_nchw_pvr(cfg, outs):

accumulator 。Tensorization on warp level schedule Motivation 全各 “The overhead of writing warp-level schedule for TensorCore 。Work at the scheduling level: level: the less the better 。 The requirement of familiarity with WMMA API “Unified matmul schedule for GPU 。 Maintainability & Common Optimization Sharing 。 Search across the entire space (TensorCore code directly from Ta ea normal thread-level schedule Se 一人一 了9 。 Normal schedule: the schedule for CUDA 本 codegen

Effective practices 1. Blameless post-mortems 2. Controlled introduction of failures for practice c. SCHEDULE BLAMELESS POST-MORTEM MEETINGS AFTER ACCIDENTS OCCUR i. Blameless Post-Mortem – meeting to examine Model – where routine and systems govern everything; including strict compliance with budget and schedule 2. Experimental Model – every day every exercise and new piece of information is evaluated and large-scale fault injection across critical systems ii. Simulate and rehearse accidents for practice 1. Schedule the event 2. Give teams time to prepare, make changes, and establish procedures 3. Execute iii

Performance AiOS 1驱动万物智能 Alios TVM @ ARM CPU INT8 Depthwise Convolution 。， NHWC layout 。 Using TVM schedule primitive completely, no tensorize 。 Some Experience: 1 Avoid DataPack 2. Generate SMLAL instruction TVM @ ARM CPU FP32 。，NHWC layout 。 For pointwise convolution we implement im2col schedule 。 No tensorize, but in schedule to cooperate with LLVM to simulate GEMM microkernel /NiiOS ! 驱动万物智能 Alios TVM jumpr r31 } PART FOUR Alios TVM @ Intel GPU AiOS 1驱动万物智能 Alios TVM @ Intel GPU 。 Implement the schedule from scratch Subgroups 。 Leverage Intel Subgroup Extension

performs poor across different shapes ○ Different templates for the same op ○ TVM compute and schedule are coupled together© 2019, Amazon Web Services, Inc. or its Affiliates. All rights reserved. Dynamic x86.schedule_conv2d_nchw) elif layout == "NHWC": strategy.register_default_implement(wrap_compute_conv2d(topi.nn.conv2d_nhwc), topi.x86.schedule_conv2d_nhwc) (wrap_compute_conv2d(topi.nn.conv2d_nchwc), topi.x86.schedule_conv2d_nchwc) else: ... return strategy© 2019, Amazon Web Services, Inc. or its Affiliates

. . . . . . . . . . . . . . . . . . . . . . . . . . . 952 47.4 Low-level synchronization using schedule and wait . . . . . . . . . . . . . . . . . . 957 48 Multi-Threading 959 48.1 Atomic operations Int" julia> g(1) "definition for Int" julia> fetch(schedule(t, 1)) "original definition" julia> t = @async f(wait()); yield(); julia> fetch(schedule(t, 1)) "definition for Int"CHAPTER 12. METHODS 160 METAPROGRAMMING 243 other similar Expr. Some examples of this include @task body which simply returns schedule(Task(() -> $body)), and @eval expr, which simply returns eval(QuoteNode(expr)). To demonstrate

. . . . . . . . . . . . . . . . . . . . . . . . . . . 952 47.4 Low-level synchronization using schedule and wait . . . . . . . . . . . . . . . . . . 957 48 Multi-Threading 959 48.1 Atomic operations Int" julia> g(1) "definition for Int" julia> fetch(schedule(t, 1)) "original definition" julia> t = @async f(wait()); yield(); julia> fetch(schedule(t, 1)) "definition for Int"CHAPTER 12. METHODS 160 METAPROGRAMMING 243 other similar Expr. Some examples of this include @task body which simply returns schedule(Task(() -> $body)), and @eval expr, which simply returns eval(QuoteNode(expr)). To demonstrate