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Basic Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2.2 Device-Limited Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2.3 Auxiliary Loss for Load affinity scores calculated for the ?-th token and all routed experts. 2.2.2. Device-Limited Routing We design a device-limited routing mechanism to bound MoE-related communication costs. When expert parallelism top-K selection among experts on these ? devices. In practice, we find that when ? ⩾ 3, the device-limited routing can achieve a good performance roughly aligned with the unrestricted top-K routing. 2.2

Lots of opportunity in PyTorch - Graph optimization - Existing fusion infrastructure fairly limited (CUDA-only, injective-only) - Kernel synthesis - Dynamic shapes, stride specialization - Impedance

measurements we track: Latency & Throughput ˃ ML pipeline contains multiple stages, performance limited by slowest one ˃ Performance results based on Xilinx own runtime pipeline available in github (https://github