Being Friendly to Your Hardware Performance Engineering A gentle introduction to hardware for software engineers 2Where does C++ run? 3On an abstract C++ machine 4On an abstract C++ machine? specialty instructions, on-core and off- core accelerators • Data layout: both software and hardware characteristics 84 src dst • Alignment: source and destination • Size • Direction • LinearityExample

faster, especially if they are compiled into a form that is directly executable on the underlying hardware. Static compilation can also devote an arbitrary amount of time to program analysis and optimization faster, especially if they are compiled into a form that is directly executable on the underlying hardware. Static compilation can also devote an arbitrary amount of time to program analysis and optimization faster, especially if they are compiled into a form that is directly executable on the underlying hardware. Static compilation can also devote an arbitrary amount of time to program analysis and optimization

layer from the hardware layerSeparate the logic layer from the hardware layer Application Layer Drivers handling LayerProcesses & Logics Separate the logic layer from the hardware layer Application Application Layer Drivers handling LayerProcesses & Logics Hardware Handling Separate the logic layer from the hardware layer Application Layer Drivers handling LayerHow are we going to test it?Probably GetNextTrafficLightLogic SetTrafficLightLogic Hardware SetTrafficLightA unit testUnit tests encourage us to keep the code simpler (Try to mock as little as possible)How Hardware tests should look like Init Write

for process data handling ▶ Provides calls for interrupt control ▶ Calls interface on interrupts ▶ Hardware concrete to the abstraction Michael Caisse Using C libraries in your Modern C++ Embedded Project libraries in your Modern C++ Embedded Project ciere.com Some Goals ▶ Testability ▶ Simulation ▶ Hardware agnostic Michael Caisse Using C libraries in your Modern C++ Embedded Project ciere.com Layered Caisse Using C libraries in your Modern C++ Embedded Project main things slushie_apphardware::hardware> app; extern "C" { void process_app(TOBJ7000 *pdo_in, TOBJ6000 *pdo_out) { auto config = t

step-by-step execution of programs; they are abstract because they omit the many details of real (hardware) machines. Abstract machines provide an intermediate language stage for compilation. They bridge N G What is an Abstract Machine? “A processor design which is not intended to be implemented as hardware, but which is the notional executor of a particular intermediate language (abstract machine language) Machine? “The C++ abstract machine is a portable abstraction of your operating system, kernel and hardware. The abstract machine is the intermediary between your C++ program and the system that it is run

the journey. • I am passionate about energy efficient computing and making the most out of older hardware, researching different platforms, tools and how to bridge different worlds and peoples together talk is an exploration of the importance of C++ as a language for writing efficient code for older hardware which is easier to access in the developing world. • It will also look into the C++ language as that everyone from a “Poor” country is “Poor” and everyone from a “Rich” Country is “Rich” Older Hardware • As TIME has progressed, Techology has improved to make SMALLER electrical components. • Meaning

::size_t>::is_always_lock_free); alignas(std::hardware_destructive_interference_size) std::atomic pushCursor_; alignas(std::hardware_destructive_interference_size) std::atomic t> popCursor_; /// Padding to avoid false sharing with adjacent objects char padding_[std::hardware_destructive_interference_size - sizeof(std::size_t)]; auto full(std::size_t pushCursor, std::size_t always_lock_free); alignas(std::hardware_destructive_interference_size) atomic pushCursor_; /// Exclusive to the push thread alignas(std::hardware_destructive_interference_size) std::size_t

Efficiency and performance ● Understanding the hardware and using it efficiently – Computing resources of a CPU – Pipelining – Branch prediction and hardware loop unrolling ● Conditional code vs efficiency evaluations/second ● Optimized: 570M evaluations/secondBranchless Computing 5 USE ALL OF THE CPU HARDWARE ALL THE TIME ● What determines performance? ● Optimal algorithm: – get the result with minimal minimal work ● Efficient use of language: – do not do any unnecessary work ● Efficient use of hardware – use all available resources – at the same time – all the timeBranchless Computing 6 GLOSSARY OF

the deal is, you only get an increase in performance, if you know how to take advantage of your hardware. Perhaps you have also heard something about the free lunch being over for programmers? In this Conversation (3/3) Each person is competing for a resource I don’t know who these people are??Does our hardware support Concurrency? Brief Architecture History 27Moore’s Law (1/2) 28 ● Around 1965 Gordon together • Heat becomes a problem • Energy consumption increases • (i.e. Dennard Scaling) So the hardware industry has adapted (effectively keeping Moore’s Law accurate) We have more smaller cpus (i

atomic_fetch_min // Member functions on atomic }Performance Considerations & Benchmark Results Hardware support can be significantly faster CAS loops have higher contention But optimized CAS can be fmaximum_num: Treat NaNs as missing data, -0 < +0. Hardware Support ● Many GPUs have native atomic float min/max ● CPU support growing (e.g. ARM v8.1) ● Hardware treats -0 < +0 and NaN as "missing data"Atomic Native atomic operations vs. CAS loops New atomic float min/max operations Semantics close to hardware capabilities Significant performance benefits Additional functions for more specific needsHazard